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tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 1 post office box 655303 ? dallas, texas 75265 2.8 v 5.5 v input voltage range programmable dual output controller supports popular dsp, fpga and microcontroller core and i/o voltages switching regulator controls i/o voltage low dropout controller regulates core voltage adjustable slow-start for simultaneous powerup of both outputs power good output monitors both outputs fast ripple regulator reduces bulk capacitance for lower system costs 1.5% reference voltage tolerance efficiencies greater than 90% overvoltage, undervoltage, and adjustable overcurrent protection drives logic level n-channel mosfets through entire input voltage range evaluation module tps56302evm163 available description the high-performance tps56302 synchronous-buck regulator provides two supply voltages to power the core and i/o of digital signal processors. the tps56302 is identical to the TPS56300 except that the reference voltages of the ldo and switching regulator have been reversed. the switching regulator, using hysteretic control with droop compensation, supports high current and efficiency for the i/o and other peripheral components. the ldo controller, suitable for powering the core voltage, drives an external n-channel power mosfet and functions as an ldo regulator and as a power distribution switch. typical design + + + u1 tps56302pwp cpc1 cpc2 vrefb vhyst droop ocp iout slowst vid0 vid1 bias vldodrv vdrv anagnd pwrpad v cc dsp v core v i/o data data bus peripheral v i (2.8 v 5.5 v) pwrgd ngateldo vsenldo inhibit ioutlo hisense highdr vsenrr losense/lohib boot bootlo lowdr drvgnd see table 1 see table 1 + + copyright ? 2000, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. powerpad is a trademark of texas instruments. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vid0 vid1 slowst vhyst vrefb vsenrr anagnd bias vldodrv cpc1 v cc cpc2 vdrv drvgnd droop ocp iout pwrgd vsenldo ngateldo inhibit ioutlo hisense losense/lohib highdr boot bootlo ldwdr pwp powerpad ? package (top view) thermal pad outputs v out ldo v out switcher tps56302 1.3 v to 2.5 v 1.3 v to 3.3 v TPS56300 1.3 v to 3.3 v 1.3 v to 2.5 v available vid code ranges note: see table 1 for actual vid codes.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 2 post office box 655303 ? dallas, texas 75265 description (continued) to promote better system reliability during power up, voltage sequencing and protection are controlled such that the core and i/o power up together with the same slow-start voltage. at power down, the ldo and ripple regulator are discharged towards ground for added protection. the tps56302 also includes inhibit, slow-start, and under-voltage lockout features to aide in controlling power sequencing. a tri-level voltage identification definition (vid) sets both regulated voltages to any of 9 preset voltage pairs from 1.3 v to 3.3 v. other voltages are possible by implementing an external voltage divider. strong mosfet drivers, with a typical peak current rating of 2-a sink and source are included on chip, which allows paralleling mosfets to be driven and allowing higher current to be controlled. the high-side driver features a floating bootstrap driver with an internal bootstrap synchronous rectifier. many protection features are incorporated within the device to ensure better system integrity. an open-drain output power good status circuit monitors both output voltages, and is pulled low if either output falls below the threshold. an over current shutdown circuit protects the high-side power mosfet against short-to-ground faults, while over voltage protection turns off the output drivers and ldo controller if either output exceeds its threshold. under voltage protection turns off the high-side and low-side mosfet drivers and the ldo controller if either output is 25% below v ref . lossless current-sensing is implemented by detecting the drain-source voltage drop across the high-side power mosfet while it is conducting. the tps56302 is fully compliant with ti dsp power requirements. available options packages t j tssop 2 (pwp) evaluation module 40 c to 125 c tps56302pwp tps56302evm163 (slvp163) 2 the pwp package is also available taped and reel. to order, add an r to the end of the part number (e.g., tps56302pwpr). table 1. voltage identification code ?# vid terminals 3 56302 56300 vid1 vid0 v refldo # (vdc) v refrr # (vdc) v refrr # (vdc) v refldo # (vdc) 0 0 1.30 1.50 1.30 1.50 0 1 1.50 1.80 1.50 1.80 0 2 1.30 1.80 1.30 1.80 1 0 1.80 3.30 1.80 3.30 1 1 1.30 1.30 1.30 1.30 1 2 2.50 3.30 2.50 3.30 2 0 1.30 2.50 1.30 2.50 2 1 1.50 3.30 1.50 3.30 2 2 1.80 2.50 1.80 2.50 3 0 = ground (gnd), 1 = floating(v bias /2), 2 = (v bias ) rr = ripple regulator, ldo = low drop-out regulator ? v bias /2 is internal, leave the vid pin floating. adding an external 0.1- m f capacitor to anagnd may be used to avoid erroneous level. # external resistors may be used as a voltage divider (from v out to vsenxx to ground) to program output voltages to other values.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 3 post office box 655303 ? dallas, texas 75265 functional block diagram cc 23 24 vldodrv ngateldo vsenldo rr_ovp ldo_ovp rr_uvp * ldo_uvp * shutdown vid 2 1 vid0 vid1 vref_ldo vref_rr 5 vrefb hysteresis setting + 28 vhyst 6 vsenrr hysteresis comparator adaptive deadtime 15 18 16 14 17 vdrv boot highdr bootlo lowdr drvgnd 22 11 inhibit v vdrv uvlo v 3 slowst shutdown + + delay 26 20 21 19 losense/ lohib ioutlo hisense iout highdr ivrefb/5 vbias 8 bias 7 reg. vldodrv 25 >0.93xvsenrr >0.93xvsenldo 4 droop pwrgd anagnd shutdown 27 125 mv ocp r s q fault latch shutdown inhibit slowst slowst shutdown shutdown 5 v 10 cpc1 9 12 cpc2 13 vdrv vdrv boot + e/a synchronous fet rrripple regulator (see table 1) vdrv * uvp is disabled during slowstart cc uvlo
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 4 post office box 655303 ? dallas, texas 75265 terminal functions terminal description name no. description vid0 1 voltage identification input 0. the vid pins are tri-level programming pins that set the output voltages for both converters. the code pattern for setting the output voltage is located in table 1. the vid pins are internally pulled to v bias /2, allowing floating voltage set to logic 1 (see table 1). vid1 2 voltage identification input 1 (see vid0 pin description and table 1). slowst 3 slow-start (soft start). a capacitor from pin 3 to gnd sets the slow-start time for v out-rr and v out-ldo . both supplies will ramp-up together while tracking the slow-start voltage. vhyst 4 hysteresis set pin. the hysteresis equals 2 (vrefb vhyst). vrefb 5 buffered ripple regulator reference voltage from vid network. vsen-rr 6 ripple regulator voltage sense input. this pin is connected to the ripple regulator output. it is used to sense the ripple regulator voltage for regulation, ovp, uvp, and power good functions.. it is recommended that an rc low pass filter be connected at this pin to filter high frequency noise. anagnd 7 analog ground bias 8 analog bias pin. recommended that a 1- m f capacitor be connected to anagnd. vldodrv 9 output of charge pump generated through bootstrap diode. approximately equal to vdrv + v in 300 mv. used as supply for ldo driver and bias regulator. recommended that a 1- m f capacitor be connected to drvgnd. cpc1 10 connect one end of charge pump capacitor. recommended that a 1- m f capacitor be connected from cpc1 to cpc2. v cc 11 3.3 v or 5 v supply (2.8 v 5.5 v). it is recommended that a low esr capacitor be connected directly from v cc to drvgnd (bulk capacitors supplied at power stage input). cpc2 12 other end of charge pump capacitor from cpc1. vdrv 13 regulated output of internal charge pump. supplies drive charge for the low-side mosfet driver (5 v). recommended that a 10- m f capacitor be connected to drvgnd. drvgnd 14 drive ground. ground for fet drivers. connect to source of low-side fet. lowdr 15 low drive. output drive to synchronous rectifier low-side fet. bootlo 16 bootstrap low. this pin connects to the junction of the high-side and low-side fets. boot 17 bootstrap pin. connect a 1- m f low esr capacitor to bootlo to generate floating drive for the high-side fet driver. highdr 18 high drive. output drive to high-side power switching fets losense/ lohib 19 low sense/low-side inhibit. this pin is connected to the junction of the high and low-side fets and is used in current sensing and the anti-cross-conduction to eliminate shoot-through current. hisense 20 high current sense. for current sensing across high-side fets, connect to the drain of the high-side fets. ioutlo 21 current sense low output. voltage on this pin is the voltage on the losense pin when the high-side fets are on. inhibit 22 this pin inhibits the drive signals to the mosfet drivers. the ic is in a low-current state if inhibit is grounded. it is recommended that an external pullup resistor be connected to 5 v. ngate-ldo 23 drives external n-channel power mosfet to regulate ldo voltage to vref-ldo. vsenldo 24 ldo voltage sense. this pin is connected to the ldo output. it is used to sense the ldo voltage for regulation, ovp, uvp, and power good functions. pwrgd 25 power good. power good signal goes high when output voltage is above 93% of v ref for both ripple regulator and ldo. this is an open-drain output. iout 26 current signal output. output voltage on this pin is proportional to the load current as measured across the high-side fets on-resistance. the voltage on this pin equals 2 r on iout, where r on is the equivalent on-resistance of the high-side fets ocp 27 over current protection. current limit trip point for ripple regulator is set with a resistor divider between the iout pin and anagnd. the trip point is typically 125 mv. droop 28 droop voltage. voltage input used to set the amount of output voltage droop as a function of load current. the amount of droop compensation is set with a resistor divider between the iout pin and anagnd.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 5 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating virtual junction temperature (unless otherwise noted) 2 supply voltage range, v cc (see note1) 0.3 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range: vdrv 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . boot to drvgnd (high-side driver on) 0.3 v to 15 v . . . . . . . . . . . . . . . . . . . . . . . . . boot to bootlo 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . boot to highdrv 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bootlo to drvgnd 0.5 v to 15 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . drv to drvgnd 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bias to anagnd 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . inhibit 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . droop 0.3 v to v cc + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ocp 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vid0, vid1 (tri-level terminals) 0.3 v to v bias + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . pwrgd 0.3 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . losense, lohib 0.5 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ioutlo 0.3 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . hisense 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vsenldo 0.3 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vsenrr 0.3 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage difference between anagnd and drvgnd 300 mv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction temperature range, t j 40 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 300 c . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: unless otherwise specified, all voltages are with respect to anagnd. dissipation rating table pwp t a < 25 c derating factor 3 t a = 70 c t a = 85 c powerpad ? mounted 3.58 w 0.0358 w/ c 1.96 w 1.43 w powerpad ? unmounted 1.78 w 0.0178 w/ c 0.98 w 0.71 w 3 test board conditions: 1.. thickness: 0.062o 2. 3o 3o 3. 2 oz. copper traces located on the top of the board (0.071 mm thick ) 4. copper areas located on the top and bottom of the pcb for soldering 5. power and ground planes, 1 oz. copper (0.036 mm thick) 6. thermal vias, 0.33 mm diameter, 1.5 mm pitch 7. thermal isolation of power plane for more information, refer to ti technical brief slma002. junction-case thermal resistance table junction-case thermal resistance 0.72 c/w
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 6 post office box 655303 ? dallas, texas 75265 electrical characteristics t j = 0 to 125 c, v cc = 2.8 v to 5.5 v (unless otherwise noted) input parameter test conditions min typ max units v cc supply voltage range 2.8 5.5 v i cc quiescent current inhibit = 0 v, v cc = 5 v 15 ma note 2: ensured by design, not production tested. reference/voltage identification parameter test conditions min typ max units vid0vid1 high-level input voltage (2) v bias 0.3 v v vid0vid1 mid-level floating voltage (1) v bias 2 1 v bias 2 1 v vid0vid1 low-level input voltage (0) 0.3 v input pull-to-mid resistance 36.5 73 95 k w cumulative reference parameter test conditions min typ max units v ref = 1.3 v, hysteresis window = 30 mv, t j = 25 c 1.3% 0.25% 1.3% cumulative accuracy ripple regulator v ref = 1.3 v, hysteresis window = 30 mv, t j = 40 c, see note 2 0.2% v ref = full range, hysteresis window = 30 mv, droop = 0, see note 2 1.5% 1.5% cumulative accuracy ldo v ref = 1.3 v, i o = 0.1 a, closed loop, pass device = irfz24n, t j = 25 c, see note 2 2% 2% y v ref = full range, i o = 0.1 a, closed loop, pass device = irfz24n, see note 2 2.5% 2.5% note 2. ensured by design, not production tested. buffered reference parameter conditions min typ max units vrefb out p ut voltage i refb =50 m a, accuracy from v ref nominal v ref 1.5% v ref v ref +1.5% v vrefb o u tp u t v oltage i refb =50 m a, accuracy from v ref nominal t j = 40 c, see note 2 v ref 0.6% v vrefb load regulation 10 m a < i refb < 500 m a 2 mv note 2. ensured by design, not production tested. hysteretic comparator(ripreg) parameter test conditions min typ max units input bias current see note 2 500 na hysteresis accuracy v vrefb v vhyst = 15 mv, hysteresis window = 30 mv 3.5 3.5 mv maximum hysteresis setting v vrefb v vhyst = 30 mv, see note 2 60 mv propagation delay time from vsense to highdr or lowdr (excluding deadtime) 10 mv overdrive, 1.3 v <= v ref <= 3.3 v, see note 2 150 250 ns prefilter pole frequency see note 2 5 mhz note 2. ensured by design, not production tested.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 7 post office box 655303 ? dallas, texas 75265 electrical characteristics t j = 0 to 125 c, v cc = 2.8 v to 5.5 v (unless otherwise noted) (continued) overvoltage protection parameter test conditions min typ max units ovp ripple regulator trip point (rr) upper threshold 112 115 120 %v ref hysteresis (rr) upper threshold lower threshold, (see note 2) 10 mv comparator propagation delay time (rr) v overdrive = 30 mv, see note 2 1 m s deglitch time (includes comparator propagation delay time) (rr) v overdrive = 30 mv, see note 2 2.25 11 m s ovp ldo trip point (ldo) upper threshold 112 115 120 % v ref hysteresis (ldo) upper threshold lower threshold, (see note 2) 10 mv comparator propagation delay time (ldo) v overdrive = 50 mv, see note 2 1 m s deglitch time (includes comparator propagation delay time) (ldo) v overdrive = 50 mv, see note 2 2.25 11 m s note 2. ensured by design, not production tested. undervoltage protection parameter conditions min typ max units uvp ripple regulator trip point (rr) lower threshold 70 75 80 % v ref hysteresis (rr) upper threshold lower threshold, (see note 2) 10 mv comparator propagation delay time (rr) v overdrive = 50 mv, see note 2 1 m s deglitch time (includes comparator propagation delay time) (rr) v overdrive = 50 mv, see note 2 0.1 1 ms uvp ldo trip point (ldo) lower threshold 70 75 80 % v ref hysteresis (ldo) upper threshold lower threshold, (see note 2) 10 mv comparator propagation delay time (ldo) v overdrive = 50 mv, see note 2 1 m s deglitch time (includes comparator propagation delay time) (ldo) v overdrive = 50 mv, see note 2 0.1 1 ms note 2. ensured by design, not production tested. inhibit comparator parameter conditions min typ max units start threshold 2.1 2.35 v start threshold t j = 40 c, see note 2 2.1 v stop threshold 1.79 v note 2. ensured by design, not production tested. vdrv uvlo parameter conditions min typ max units start threshold see note 2 4.9 v hysteresis see note 2 0.3 0.35 v stop threshold see note 2 4.4 v note 2. ensured by design, not production tested.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 8 post office box 655303 ? dallas, texas 75265 electrical characteristics t j = 0 to 125 c, v cc = 2.8 v to 5.5 v (unless otherwise noted) (continued) slow-start parameter conditions min typ max units charge current v (s/s) = 0.5 v, resistance from vrefb pin to anagnd = 20 k w vrefb = 1.3 v, ichg = (i vrefb /5) 10.4 13 15.6 m a discharge current v (s/s) = 1.3 v 3 ma comparator input offset voltage 10 mv comparator input bias current see note 2 10 100 na hysteresis accuracy 7.5 7.5 mv comparator propagation delay overdrive = 10 mv, see note 2 560 1000 ns note 2. ensured by design, not production tested. v cc uvlo parameter conditions min typ max units start threshold (see note 2) 2.72 2.80 v start threshold t j = 40 c, see note 2 2.71 v stop threshold (see note 2) 2.48 v note 2. ensured by design, not production tested. power good parameter conditions min typ max units undervoltage trip point ripple regulator v in and vdrv above uvlo thresholds 90 93 95 %v ref gg (vsenserr) t j = 40 c, see note 2 93 % v ref undervoltage trip point ldo v in and vdrv above uvlo thresholds 90 93 95 %v ref g (vsenseldo) t j = 40 c, see note 2 93 % v ref output saturation voltage i o =5 ma 0.5 0.75 v leakage current v pgd = 4.5 v 1 m a hysteresis v ref = 1.3 v, 1.5 v, or 1.8 v 50 75 mv h y steresis v ref = 2.5 v, or 3.3 v 100 125 mv comparator highlow transition time (propagation delay only) see note 2 1 m s comparator lowhigh transition time (propagation delay + deglitch) see note 2 0.2 1 2 ms note 2. ensured by design, not production tested. droop compensation parameter conditions min typ max units initial accuracy v droop = 50 mv 46 54 mv overcurrent protection (rr) parameter conditions min typ max units ocp trip point 118 130 142 mv input bias current 300 na comparator propagation delay time v overdrive = 30 mv, see note 2 1 m s deglitch time (includes comparator propagation delay time) v overdrive = 30 mv, see note 2 2.25 11 m s note 2. ensured by design, not production tested.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 9 post office box 655303 ? dallas, texas 75265 electrical characteristics t j = 0 to 125 c, v cc = 2.8 v to 5.5 v (unless otherwise noted) (continued) high-side vds sensing parameter conditions min typ max units gain 2 v/v initial accuracy v hisense = 3.3 v, v ioutlo = 3.2 v, differential input to vds sensing amp = 100 mv 194 208 mv common-mode rejection ratio v hisense =2.8 v to 5.5 v, v hisense v ioutlo =100 mv 69 75 db sink current (ioutlo) 2.8 v < v ioutlo < 5.5 v 250 na source current (iout) v iout = 0.5 v, v hisense =3.3 v, v ioutlo =2.8 v 500 m a sink current (iout) v iout = 0.05 v, v hisense =3.35 v, v ioutlo =3.3 v 50 m a v hisense =5.5 v, r iout = 10 k w 0 1.75 output voltage swing v hisense =4.5 v, r iout = 10 k w 0 1.5 v v hisense =3 v, r iout = 10 k w 0 0.75 losense high-level input voltage v hisense =2.8 v, see note 2 1.77 v losense low-level input voltage v hisense =2.8 v, see note 2 1.49 v losense high-level input voltage v hisense =4.5 v, see note 2 2.85 v losense low-level input voltage v hisense =4.5 v, see note 2 2.4 v losense high-level input voltage v hisense =5.5 v, see note 2 3.80 v losense low-level input voltage v hisense =5.5 v, see note 2 3.2 v v hisense = 6 v, see note 2 70 90 sam p le/hold resistance v hisense = 4.5 v, see note 2 80 100 w sample/hold resistance v hisense = 3.6 v, see note 2 90 120 w v hisense = 2.8 v, see note 2 120 180 v hisense = 2.55 v, v ioutlo pulsed from 2.55 v to 2.45 v, 100 ns rise and fall times, see note 2 4 response time (measured from 90% of v hisense = 2.8 v, v ioutlo pulsed from 2.8 v to 2.7 v, 100 ns rise and fall times, see note 2 3.5 m s ( v ioutlo to 90% of v iout ) v hisense = 4.5 v, v ioutlo pulsed from 4.5 v to 4.4 v, 100 ns rise and fall times, see note 2 3 m s v hisense = 5.5 v, v ioutlo pulsed from 5.5 v to 5.9 v, 100 ns rise and fall times, see note 2 3 short circuit protection rising edge delay losense grounded, see note 2 300 500 ns sample/hold switch turnon/turnoff delay 2.8 v < v hisense < 5.5 v, v losense = v hisense , see note 2 30 100 ns note 2. ensured by design, not production tested.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 10 post office box 655303 ? dallas, texas 75265 electrical characteristics t j = 0 to 125 c, v cc = 2.8 v to 5.5 v (unless otherwise noted) (continued) thermal shutdown parameter conditions min typ max units over temperature trip point see note 2 145 c hysteresis see note 2 10 c note 2. ensured by design, not production tested. synch charge pump regulator parameter conditions min typ max units internal oscillator frequency 2.8 v < v in < 5.5 v, i drv = 50 ma, vdrv=5 v , see note 2 200 300 400 khz internal oscillator turnon threshold v cc above uvlo threshold, see note 2 5.05 5.2 v internal oscillator turnon hysteresis v cc above uvlo threshold, see note 2 20 mv note 2. ensured by design, not production tested. hysteretic comparator (charge pump) parameter conditions min typ max units threshold v in above uvlo threshold, see note 2 5.05 5.2 v hysteresis v in above uvlo threshold, see note 2 20 mv note 2. ensured by design, not production tested. deadtime circuit parameter conditions min typ max units losense/lohib high level input voltage v hisense =2.55 v 5.5 v, see note 2 2.4 v losense/lohib low level input voltage v hisense =2.55 v 5.5 v, see note 2 1.33 v lowdr high level input voltage v hisense =2.55 v5.5 v, see note 2 3 v lowdr low level input voltage v hisense =2.55 v5.5 v, see note 2 1.7 v driver nonoverlap time c lowdr = 9 nf, 10% threshold on lowdr, vdrv=5 v 40 170 ns note 2. ensured by design, not production tested.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 11 post office box 655303 ? dallas, texas 75265 electrical characteristics t j = 0 to 125 c, v cc = 2.8 v to 5.5 v (unless otherwise noted) (continued) output drivers (see note 5) parameter conditions min typ max units duty cycle < 2%, t pw < 100 us, v boot v bootlo = 4.5 v, v highdr = 4 v (sink), see note 2 and figure 15 0.7 2 peak out p ut current duty cycle < 2%, t pw < 100 us, v boot v bootlo = 4.5 v, v highdr = 0.5 v (source), see note 2 and figure 15 1.2 2 a peak o u tp u t c u rrent duty cycle < 2%, t pw < 100 m s, v drv = 4.5 v, v lowdr = 4 v (sink), see note 2 and figure 15 1.3 2 a duty cycle < 2%, t pw < 100 us, v drv = 4.5 v, v lowdr = 0.5 v (source), see note 2 and figure 15 1.4 2 v boot v bootlo = 4.5 v, v highdr = 0.5 v, see note 2 5 output resistance v boot v bootlo = 4.5 v, v highdr = 4 v, see note 2 45 w v drv = 4.5 v, v lowdr = 0.5 v, see note 2 9 v drv = 4.5 v, v lowdr = 4 v, see note 2 45 highdr rise/fall time c l = 3.3 nf, v boot = 4.5 v, v bootlo =grounded, see note 2 60 ns lowdr rise/fall time c l = 3.3 nf, v drv = 4.5 v, see note 2 40 ns inhibit grounded, v in < uvlo, v boot =6 v, bootlo grounded 10 m a high-side driver quiescent current inhibit connected to +5 v, v in > uvlo f (swx) = 200 khz, v boot = 5.5 v, bootlo = 0, c highdr = 50 pf, see note 2 2 ma notes: 2. ensured by design, not production tested. 5. the pullup/pulldown circuits of the drivers are bipolar and mosfet transistors in parallel. the peak output current rating is the combined current from the bipolar and mosfet transistors. the output resistance is the r ds(on) of the mosfet transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. ldo n-channel output driver parameter conditions min typ max units peak out p ut current v ldodrv = 7.5 v, v ndrv = 3 v (source), v iosense = 0.9 v ldoref , see note 2 100 m a peak o u tp u t c u rrent v ldodrv = 7.5 v, v ndrv =0 v (sink), v iosense = 1.1 v ldoref , see note 2 1.5 ma open loop voltage gain (v ngateldo / v senseldo ) 7.5 v v ngateldo 0.5 v, v in = 5.5 v, see note 2 3000 (70) v/v (db) power supply ripple rejection f = 1 khz, c o =10 m f, 5.5 v v in 2.55 v, t j =125 c, see note 2 60 db note 2. ensured by design, not production tested.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 12 post office box 655303 ? dallas, texas 75265 electrical characteristics t j = 0 to 125 c, v cc = 2.8 v to 5.5 v (unless otherwise noted) (continued) v senserr and v senseldo discharge parameter conditions min typ max units v senserr discharge fet current saturation v senserr = 1.5 v, see note 2 5 ma v senserr discharge series resistance (limits current) inhibit = 0 v, v in = 5.5 v 1 k w v senserr discharge fet propagation delay time see note 2 100 ns v senseldo discharge fet current saturation v senseldo = 3.3 v, see note 2 5 ma v senseldo discharge series resistance (limits current) inhibit = 0 v, v in = 5.5 v, 1 k w v senseldo discharge fet propagation delay time see note 2 100 ns note 2. ensured by design, not production tested. detailed description reference/voltage identification the reference/voltage identification definition (vid) section consists of a temperature compensated bandgap reference and a 2-pin voltage selection network. both ripple regulator and ldo reference voltages are programmed with each vid setting. the 2 vid pins are inputs to the vid selection network and are tri-level inputs that may be set to gnd, floating (v bias /2), or v bias . the vid codes allow the controller to power both current and future dsp products. the output voltages may also be programmed by external resistor voltage dividers for any values not included in the vid code settings. refer to table 1 for the vid code settings. the output voltages of the vid network, v refrr , is within 1.5% and v refldo is within 2.5% of the nominal setting over the vid range of 1.3 v to 3.3 v. the reference tolerance conditions include a junction temperature range of 40 c to +125 c and a v cc supply voltage range of 2.8 v to 5.5 v. the v refrr output of the reference/vid network is indirectly brought out through a buffer to the vrefb pin. the voltage on this pin will be within 1.5% of v refrr . it is not recommended to drive loads with vrefb, other than setting the hysteresis of the hysteretic comparator, because the current drawn from vrefb sets the charging current for the slow-start capacitor. refer to the slow-start section of this document for additional information. hysteretic comparator the hysteretic comparator regulates the output voltage of the synchronous-buck converter. the hysteresis is set by 2 external resistors and is centered around v ref . the two external resistors form a resistor divider from vrefb to anagnd, and the divided down voltage connects to the vhyst pin. the hysteresis of the comparator will be equal to twice the voltage difference that is across the vrefb and vhyst pins. the propagation delay from the comparator inputs to the driver outputs is 250 ns maximum. the maximum hysteresis setting is 60 mv. low-side driver the low-side driver is designed to drive low r ds(on) logic-level n-channel mosfets. the current rating of the driver is 2-a typical, source and sink. the bias to the low-side driver is internally connected to the regulated synchronous charge pump output. high-side driver the high-side driver is designed to drive low r ds(on) logic-level n-channel mosfets. the current rating of the driver is 2 amps typical, source and sink. the high-side driver can be configured either as a floating bootstrap driver or as a ground-reference driver. when configured as a floating driver, the bias voltage to the driver is developed from the charge pump vdrv voltage. the internal synchronous bootstrap rectifier, connected between the vdrv and boot pins, is a synchronously-rectified mosfet for improved drive efficiency. the maximum voltage that can be applied between the boot pin and ground is 14 v.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 13 post office box 655303 ? dallas, texas 75265 detailed description (continued) deadtime control deadtime control prevents shoot-through current from flowing through the main power fets during switching transitions by actively controlling the turnon time of the mosfet drivers. the high-side driver is not allowed to turn on until the gate drive voltage to the low-side fet is below 1 v, and the low-side driver is not allowed to turn on until the voltage at the junction of the 2 fets (vphase) is below 2 v. current sensing current sensing is achieved by sampling and holding the voltage across the high-side power fet while the high-side fet is on. the sampling network consists of an internal 60- w switch and an external hold capacitor. internal logic controls the turnon and turnoff of the sample/hold switch such that the switch does not turn on until the vphase voltage transitions high, and the switch turns off when the input to the high-side driver goes low. thus sampling will occur only when the high-side fet is conducting current. the voltage on the iout pin equals 2 times the sensed high-side voltage. droop compensation the droop compensation network reduces the load transient overshoot / undershoot on v out , relative to v ref (see the application information section of this document for more details). v out is programmed to a voltage greater than v ref by an external resistor divider from v out to the vsense pin to reduce the undershoot on v out during a low to high load transient. the overshoot during a high to low load transient is reduced by subtracting the voltage that is on the droop pin from v ref . the voltage on the iout pin is divided down with an external resistor divider, and connected to the droop pin. inhibit inhibit is a ttl-compatible comparator pin that is used to enable the controller. when inhibit is lower than the threshold, the output drivers are low and the slow-start capacitor is discharged. when inhibit goes high (above 2.1 v), the short across the slow-start capacitor is released and normal converter operation begins. when another system logic supply is connected to the inhibit pin, this pin controls power sequencing by locking out controller operation until the system logic supply exceeds the input threshold voltage of the inhibit circuit; thus the +3.3-v supply and another system logic supply (either +5 v or +12 v) must be above uvlo thresholds before the controller is allowed to start up. toggling the inhibit pin from low to high or recycling v cc clears the fault latch. slow-start the slow-start circuit controls the rate at which both v outrr and v outldo power up (at the same time). a capacitor is connected between the slowst and anagnd pins and is charged by an internal current source. the value of the current source is proportional to the reference voltage, so that the charging rate of c slowst is proportional to the ripple regulator reference voltage. the slow-start charging current is determined by the following equation: i slowstart i vrefb 5 where i vrefb is the current flowing out of the vrefb pin. it is recommended that no additional loads be connected to vrefb, other than the resistor divider for setting the hysteresis voltage. thus these resistor values will determine the slow-start charging current. the maximum current that can be sourced by the vrefb circuit is 500 m a. the equation for the slow-start time is: t slowstart 5 c slowstart r vrefb where r vrefb is the total external resistance from vrefb to anagnd.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 14 post office box 655303 ? dallas, texas 75265 detailed description (continued) v cc and vdrv undervoltage lockout the v cc undervoltage lockout circuit disables the controller while the v cc supply is below the 2.8-v start threshold. the vdrv undervoltage lockout circuit disables the controller while the vdrv supply is below the 4.9 v start threshold during powerup. while the controller is disabled, the output drivers will be low, the ldo drive is off, and the slow-start capacitor will be shorted. when v cc and vdrv exceed the start threshold, the short across the slow-start capacitor is released and normal converter operation begins. recycling v cc or toggling the inhibit pin from low to high clears the fault latch. power good the power good circuit monitors for an undervoltage condition on v outrr and v outldo . the power good (pwrgd) pin is pulled low if either v outrr is 7% below v refrr , or v outldo is 7% below v refldo . pwrgd is an open drain output. the pwrgd pin is also pulled down, if either v cc or vdrv are below their uvlo thresholds. overvoltage protection the overvoltage protection circuit monitors v outrr and v outldo for an overvoltage condition. if v outrr or v outldo are 15% above their reference voltage, then a fault latch is set and both output drivers and ldo are turned off. the latch remains set until the v cc or inhibit voltages go below their undervoltage lockout turnoff values. a 1- m s to 5 m s deglitch timer is included for noise immunity. overcurrent protection the overcurrent protection circuit monitors the current through the high-side fet. the overcurrent threshold is adjustable with an external resistor divider between iout and anagnd pins, with the divider voltage connected to the ocp pin. if the voltage on the ocp pin exceeds 125 mv, a fault latch is then set and the output drivers are turned off. the latch remains set until the v cc or inhibit voltages go below their undervoltage lockout values. a 1- m s to 5- m s deglitch timer is included for noise immunity. the ocp circuit is also designed to protect the high-side power fet against a short-to-ground fault on the terminal common to both power fets. undervoltage protection the undervoltage protection circuit monitors v outrr and v outldo for an undervoltage condition. if v outrr or v outldo is 15% below their reference voltage, then a fault latch is set and both output drivers and ldo are turned off. the latch remains set until the v cc or inhibit voltages go below their undervoltage lockout values. a 100- m s to 1-ms deglitch timer is included for noise immunity. synchronous charge pump the regulated synchronous charge pump provides drive voltage to the low-side driver at vdrv (5 v), and to the high-side driver configured as a floating driver. the minimum drive voltage is 4.5 v, (typical is 5 v). the minimum short-circuit current is 80 ma. the bootstrap capacitor is used to provide voltage for the high-side fet, the power for vldodrv, and the bias regulator. instead of diodes, synchronous rectified mosfets are used to reduce voltage drop losses and allow a lower input voltage threshold. the charge pump oscillator operates at 300 khz until the uvlo vdrv is set; after which it is synchronized to the converter switching frequency and is turned on and off to regulate vdrv at 5 v. the charge pump is designed to operate at a switching frequency of 200 khz to 400 khz. operation at low frequency may require larger capacitors on the cpcx and vdrv pins. higher frequencies (> 400 khz) may not be possible. power sequence the v outldo voltage is powered up with respect to the same slow-start reference voltage as the v outrr also, at power down, the v outrr and v outldo are discharged to ground through p-channel mosfets in series with 1-k w resistors.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 15 post office box 655303 ? dallas, texas 75265 typical characteristics figure 1 10 11 12 13 0 25 50 75 100 125 quiescent current ma quiescent current vs junction temperature t j junction temperature c v cc = 3.3 v inhibit = 0 v figure 2 150 155 160 165 170 175 180 0 25 50 75 100 125 v cc uvlo hysteresis vs junction temperature t j junction temperature c uvlo hysteresis mv v cc figure 3 2.65 2.675 2.700 2.725 2.750 0 25 50 75 100 125 v cc uvlo start threshold voltage vs junction temperature t j junction temperature c uvlo start threshold voltage v v cc figure 4 t j junction temperature c slow-start charge current vs junction temperature 12 10 25 75 14 13 11 50 100 125 15 0 slowstart charge current a m
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 16 post office box 655303 ? dallas, texas 75265 typical characteristics figure 5 slow-start time vs supply current (vrefb) 110 i cc supply current (vrefb) m a 1000 1 10 slowstart time ms v cc = 3.3 v v (vrefb) = 1.3 v c s = 0.1 m f t j = 27 c 100 1000 100 figure 6 slow-start time 2 vs slow-start capacitance 0.0001 0.0010 slow-start capacitance m f 100 10 1 0.1 slowstart time ms v cc = 3.3 v v (vrefb) = 1.3 v i (vrefb) = 65 m a t j = 25 c 0.0100 0.1000 1 figure 7 driver rise time vs gate capacitance 0.1 1 gate capacitance nf 100 1 10 rise time ns 10 100 t r 1000 t j = 27 c high side low side figure 8 gate capacitance nf 0.1 1 1000 1 10 10 100 100 fall time ns t f driver fall time vs gate capacitance t j = 27 c high side low side
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 17 post office box 655303 ? dallas, texas 75265 typical characteristics figure 9 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 25 50 75 100 125 driver high-side output resistance vs junction temperature t j junction temperature c high-side output resistance r o w figure 10 0 1 2 3 4 5 6 7 8 0 25 50 75 100 125 driver low-side output resistance vs junction temperature t j junction temperature c low-side output resistance r o w figure 11 input current a driver current vs output voltage v o output voltage v 1 0 13 2 1.5 0.5 245 2.5 0 3 7 689 4 3.5 4.5 5 2 a typical 4.5 v figure 12 4.65 4.66 4.67 4.68 4.69 4.70 0 25 50 75 100 125 vdrv uvlo start threshold voltage v vdrv uvlo start threshold voltage vs junction temperature t j junction temperature c
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 18 post office box 655303 ? dallas, texas 75265 typical characteristics figure 13 100 120 140 160 180 200 220 240 260 280 300 0 25 50 75 100 125 vdrv uvlo hysteresis mv vdrv uvlo hysteresis vs junction temperature t j junction temperature c figure 14 88 89 90 91 92 93 94 95 96 0 25 50 75 100 12 5 ripple regulator powergood threshold % ripple regulator power good threshold vs junction temperature t j junction temperature c figure 15 2.000 2.025 2.050 2.075 2.100 0 25 50 75 100 125 inhibit start threshold voltage v inhibit start threshold voltage vs junction temperature t j junction temperature c figure 16 90 100 110 120 130 140 0 25 50 75 100 125 inhibit hysteresis voltage mv inhibit hysteresis voltage vs junction temperature t j junction temperature c
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 19 post office box 655303 ? dallas, texas 75265 typical characteristics figure 17 t j junction temperature c ripple regulator ovp threshold vs junction temperature 114 112 25 75 116 115 113 50 100 125 117 0 ripple regulator ovp threshold % 118 figure 18 t j junction temperature c ripple regulator uvp threshold vs junction temperature 73 71 25 75 75 74 72 50 100 125 76 0 ripple regulator uvp threshold % 77 t j junction temperature c ocp threshold voltage vs junction temperature 129 25 75 133 131 50 100 125 135 0 ocp treshhold voltage mv figure 19
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 20 post office box 655303 ? dallas, texas 75265 typical characteristics 112 113 114 115 116 117 118 0 25 50 75 100 125 ldo ovp threshold % ldo ovp threshold vs junction temperature t j junction temperature c figure 20 t j junction temperature c ldo uvp threshold vs junction temperature 73 71 25 75 75 74 72 50 100 125 76 0 ldo uvp threshold % 77 figure 21
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 21 post office box 655303 ? dallas, texas 75265 application information evaluation module in many dsp applications, the voltage bus powering dsp i/o also has to power peripheral circuitry. the total current is much higher than the requirement for the i/o only. this is the reason to use the high-efficiency ripple regulator to power i/o. in turn, the core power is delivered by ldo output. since the i/o voltage is lower than the input voltage in cases such as 5-v input, but higher than the core voltage, the ripple regulator output should be used as the input voltage for ldo to achieve higher efficiency. in evm testing, j14 (rrout) is connected to j21(vildo). the test results displayed in this section are all based on this configuration. jp2 jp1 pwrpad u1 tps563xxpwp jp3 tp8 tp7 e1 q1:a q4 tp11 tp3 tp1 q1:b q5 + tp2 fb2 j2 + + tp6 tp5 fb1 + + + tp10 + l1 3.3 uh + + tp4 j1 figure 22. evm schematic table 2. evm input and outputs v in i in v rr i rr v ldo i ldo 5 v 4 a 3.3 v 4 a 1.8 v 0.5 a
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 22 post office box 655303 ? dallas, texas 75265 application information table 3. ripple regulator power stage components ripple regulator section ref des function 4a (evm design) 8a 2 12a 2 20a 2 c3, c6 input bulk capacitor c3: open c6: 150 m f (sanyo, 6tpb150m) c3: 150 m f c6: 150 m f (sanyo, 6tpb150m) c3: 150 m f c6: 150 m f (sanyo, 6tpb150m) c3: 150 m f c6: 2x150 m f (sanyo, 6tpb150m) c11, c2 input high-freq capacitor c2: 0.1 m f c11: 0.1 m f (murata grm39x7r104k016a, 0.1 m f, 16v, x7r) c2: 0.1 m f c11: 0.1 m f (murata grm39x7r104k016a, 0.1 m f, 16v, x7r) c2: 0.1 m f c11: 0.1 m f (murata grm39x7r104k016a, 0.1 m f, 16v, x7r) c2: 0.33 m f c11: 0.33 m f (murata grm39x7r334k016a, 0.33 m f, 16v, x7r) c13, c14 output bulk capacitor c13: 150 m f (sanyo, 6tpb150m) c14: open c13: 150 m f (sanyo, 6tpb150m) c14: open c13: 150 m f c14: 150 m f (sanyo, 6tpb150m) c13: 150 m f c14: 150 m f (sanyo, 6tpb150m) c15,c30, c31 output mid-freq capacitor c15: open c30: 10 m f c31: 10 m f (murata grm39x7r106k016a, 10 m f, 16v, x7r) c15: open c30: 10 m f c31: 10 m f (murata grm39x7r106k016a, 10 m f, 16v, x7r) c15: 10 m f c30: 10 m f c31: 10 m f (murata grm39x7r106k016a, 10 m f, 16v, x7r) c15: 10 m f c30: 10 m f c31: 10 m f (murata grm39x7r106k016a, 10 m f, 16v, x7r) c16 output high-freq capacitor open 0.1 m f (murata grm39x7r104k016a, 0.1 m f, 16v, x7r) 0.1 m f (murata grm39x7r104k016a, 0.1 m f, 16v, x7r) 0.1 m f (murata grm39x7r104k016a, 0.1 m f, 16v, x7r) l1 input filter 3.3 m h coilcraft do3316p332, 5.4 a 3.3 m h coilcraft do3316p332,5.4 a 1.5 m h coilcraft do3316p152,6.4 a 1 m h coiltronics up3b1r0, 12.5a l2 output filter 3.3 m h coilcraft do3316p332, 5.4 a 3.3 m h coilcraft do5022p332hc, 10 a 1.5 m h coilcraft do5022p152hc, 15 a 3.3 m h micrometals, t688/90 core w/7t, #16, 25 a r8 low side gate resistor 10 w 10 w 5.1 w 5.1 w q1a,q4 power switch q1a: dual fet irf7311 q4: irf7811 q4: 2xirf7811 q4: 2xirf7811 q1b,q5 synchronous switch q1b: dual fet irf7311 q5: irf7811 q5: 2xirf7811 q5: 2xirf7811 2 position available on the evm board the values listed in table 3 are recommendations based on actual test circuits. many variations of the above are possible based upon the desires and/or requirements of the user. performance of the circuit is equally, if not more, dependent upon the layout than on the specific components, as long as the device parameters are not exceeded. fast-response, low-noise circuits require circuits require critical attention to the layout details.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 23 post office box 655303 ? dallas, texas 75265 application information table 4. ldo power stage components ldo section ref. des part v in v out description q2:a irf7811(evm) or si4410, irf7413 3 fds6680 v in v in v dropout 2 used as a power distribution switch for ldo output control q2:a irf9410, si9410 3 low cost solution for low ldo output cur- rent (v in v out )*i out < 1 w q2:a irf7811 3 higher current and still surface mount 1 w < (v in v out )*i out ) < 2 w q2: b irlz24n 3 high output current requiring heat sink. low cost but throughhole package. (v in v out )*i out > 2 w 2 v dropout = i out rdson. it should be as small as possible. 3 position available on the evm board frequency calculation with hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the hysteresis window, the delay of the hysteresis comparator and the driver, the output inductance, the resistance in the output inductor, the output capacitance, the esr and esl in the output capacitor, the output current, and the turnon resistance of high-side and low-side mosfet. it is a very complex equation if everything is included. to make it more useful to designers, a simplified equation is developed that considers only the most influential factors. the tolerance of the result for this equation is about 30%: f s v out v in v out
esr 250 10 9 t d c out
v in v in esr 250 10 9 t d v hys l out esl v in where f s is the switching frequency (hz); v out is the output voltage (v); v in is the input voltage (v); c out is the output capacitance; esr is the equivalent series resistance in the output capacitor ( w ); esl is the equivalent series inductance in the output capacitor (h); l out is the output inductance (h); t d is output feedback rc filter time constant (s); v hys is the hysteresis window (v). output voltage setpoint calculation in some applications, the required output voltage is different from the vid reference voltage. in this case, external voltage divider can be used for the setpoint adjustment. the voltage divider is composed of two resistors. the equation for the setpoint is: r bottom r top v r v o v r where v r is the reference voltage; v o is the required output voltage setpoint. v r should be lower than v o . in evm design, the top resistor is r14 for the ldo output, or r10 for ripple regular output; the bottom resistor is r15 for ldo output, or r12 for ripple regulator output.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 24 post office box 655303 ? dallas, texas 75265 application information hysteresis window the changeable hysteresis window in tps56302 is used for switching frequency and output voltage ripple adjustment. the hysteresis window setup is decided by a two-resistor voltage divider on vrefb and vhyst pin. two times the voltage drop on the top resistor is the hysteresis window. the formula is shown in the following: ) 13 r 11 r 13 r 1 ( vrefb 2 + = v hyswindow where v hyswindow is the hysteresis window (v); vrefb is the regulated voltage from vrevb (pin 5); r11 is the top resistor in the voltage divider; r13 is the bottom resistor in the voltage divider. the maximum hysteresis window is 60 mv. slow-start slow-start reduces the start-up stresses on the power-stage components and reduces the input current surge. the minimum slow-start time is limited to 1 ms due to the power good function deglitch time. slow-start timing is dependent on the timing capacitor value on the slow-start pin and the total resistance on vrefb. the following formula can be used for setting the slow-start timing: t slow-start 5 c slow-start r vrefb t slow-start is the slow-start time; c slow-start is the capacitor value on slowst (pin 3). r vrefb is the total resistance on vrefb (pin 5). current limit current limit is implemented using the on-resistance of the upper fets as the sensing elements. the iout signal is used for the current limit and the droop function. the voltage at iout at the output current trip point will be: v iout r on i o 2 r on is the high-side on-time resistance; i o is the output current. the current limit is calculated by using the equation: r5 r4 i o max 2 r on 0.125 0.125 where r4 is the bottom resistor in the voltage divider on ocp pin, and r5 is the top resistor; i o(max) is the maximum current allowed; r on is the high-side fet on-time resistance. since the fet on-time resistance varies according to temperature, the current limit is basically for catastrophic failure.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 25 post office box 655303 ? dallas, texas 75265 application information droop compensation droop compensation with the offset resistor divider from v out to the vsense is used to keep the output voltage in range during load transients by increasing the output voltage setpoint toward the upper tolerance limit during light loads and decreasing the voltage setpoint toward the lower tolerance limit during heavy loads. this allows the output voltage to swing a greater amount and still remain within the tolerance window. the maximum droop voltage is set with r6 and r7: v droop max v iout max r6 r6 r7 where v droop(max) is the maximum droop voltage; v iout(max) is the maximum v iout that reflects the maximum output current (full load); r6 is the bottom resistor of the divider connected to the droop pin, r7 is the top resistor. the offset voltage is set to be half of the maximum droop voltage higher than the nominal output voltage, so the whole droop voltage range is symmetrical to the nominal output voltage. the formula for setting the offset voltage is: v offset 1 2 v droop max v o r12 r10 r12 where v offset is the desired offset voltage; v droop(max) is the droop voltage at full load; v o is the nominal output voltage; r10 is the top resistor of the offset resistor divider, and r12 is the bottom one. therefore, with the setup above, at light load, the output voltage is: v o no load v o nom v offset v o nom 1 2 v droop and, at full load, the output voltage is: v o full load v o nom v offset v o nom 1 2 v droop output inductor ripple current the output inductor current ripple can affect not only the efficiency, but also the output voltage ripple. the equation for calculating the inductor current ripple is exhibited in the following: i ripple v in v out i out r ds(on) r l l out d ts where i ripple is the peak-to-peak ripple current (a) through the inductor; v in is the input voltage (v); v out is the output voltage (v); i out is the output current; r ds(on) is the on-time resistance of mosfet ( w ); r l is the output inductor equivalent series resistance; d is the duty cycle; and ts is the switch cycle (s). from the equation, it can be seen that the current ripple can be adjusted by changing the output inductor value. example: v in = 5 v; v out = 1.8 v; i out = 5 a; r ds(on) = 10 m w ; r l = 5 m w ; d = 0.36; ts = 5 m s; l out = 6 m h then, the ripple i ripple = 1 a.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 26 post office box 655303 ? dallas, texas 75265 application information output capacitor rms current assuming the inductor ripple current totally goes through the output capacitor to ground, the rms current in the output capacitor can be calculated as: 12 i i d = o(rms) where i o(rms) is the maximum rms current in the output capacitor (a); d i is the peak-to-peak inductor ripple current (a). example: d i = 1 a, so i o(rms) = 0.29 a input capacitor rms current the input capacitor rms current is important for input capacitor design. assuming the input ripple current totally goes into the input capacitor to the power ground, the rms current in the input capacitor can be calculated as: i i(rms) i o 2 d ( 1 d ) 1 12 d i ripple 2 where i i(rms) is the input rms current in the input capacitor (a); i o is the output current (a); i ripple is the peak-to-peak output inductor ripple current; d is the duty cycle. from the equation, it can be seen that the highest input rms current usually occurs at the lowest input voltage, so it is the worst case design for input capacitor ripple current. example: i o = 5 a; d = 0.36; i ripple = 1 a, then, i i(rms) = 2.46 a layout and component value consideration good power supply results will only occur when care is given to proper design and layout. layout and component value will affect noise pickup and generation and can cause a good design to perform with less than expected results. with a range of current from milliamps to tens or even hundreds of amps, good power supply layout and component selection, especially for a fast ripple controller, is much more difficult than most general pcb design. the general design should proceed from the switching node to the output, then back to the driver section, and, finally, to placing the low-level components. in the following list are several specific points to consider before layout and component selection for tps56302: 1. all sensitive analog components should be referenced to anagnd. these include components connected to slowst, droop, iout, ocp, vsense, vrefb, vhyst, bias, and losense/lohib. 2. the input voltage range for tps56302 is low from 2.8-v to 5.5-v, so it has a voltage tripler (charge pump) inside to deliver proper voltage for internal circuitry. to avoid any possible noise coupling, a low esr capacitor on v cc is recommended. 3. for the same reason in item 2, the anagnd and drvgnd should be connected as close as possible to the ic. 4. the bypass capacitor should be placed close to the tps56302.
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 27 post office box 655303 ? dallas, texas 75265 application information layout and component value consideration (continued) 5. when configuring the high-side driver as a boot-strap driver, the connection from bootlo to the power fets should be as short and as wide as possible. losense/lohib should have a separate connection to the fets since bootlo will have large peak current flowing through it. 6. the bulk storage capacitors across v in should be placed close to the power fets. high-frequency bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the high-side fet and to the source of the low-side fet. 7. hisense and losense/lohib should be connected very close to the drain and source, respectively, of the high-side fet. hisense and losense/lohib should be routed very close to each other to minimize differential-mode noise coupling to these traces. ceramic decoupling capacitors should be placed close to where hisense connects to v in , to reduce high-frequency noise coupling on hisense. the evm board (slvp-139) is used in the test. the test results are shown in the following. figure 23 i o output current a efficiency of ripple regulator (3.3 v) 60 40 13 80 70 50 245 100 0 efficiency % 90 v in = 5 v figure 24 i o output current a ripple regulator load regulation (3.3 v) 2 13 0 1 245 1 0 2 v in = 5 v load regulation %
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 28 post office box 655303 ? dallas, texas 75265 application information figure 25 0 1 v in input voltage v ripple regulator line regulation (3.3 v) 1 2 35 2 46 line regulation % 3.5 4.5 5.5 i o = 2 a i o output current a figure 26 ldo load regulation (1.8 v) 2 1 0 0 1 2 0.2 0.8 0.4 0.6 1.2 1 line regulation % v in = 5 v figure 27 droop compensation effect 280 mv 220 mv with droop no droop output voltage t time ms 0 1.5 1 0.5 2 2.5 3.5 3 4 4.5 5 i load current a l 200 100 0 0 5 10 5 output voltage mv v o 100 t time ms 012 8 4162028 24 32 36 40 3.3 v 1.8 v 1 0 4 1 5 6 3 2 output voltage v v o 2 slow-start figure 28
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 29 post office box 655303 ? dallas, texas 75265 application information layouts 3 in 2.7 in figure 29. top layer figure 30. bottom layer (top view)
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 30 post office box 655303 ? dallas, texas 75265 application information bill of materials ref pn description mfg size c1 10tpa33m capacitor, poscap, 33 m f, 10 v sanyo c c2, c20, c21, c30, c31 std capacitor, ceramic, 10 m f, 16 v sanyo 1210 c3. c6, c8, c13, c25 6tpb150m capacitor, poscap, 150 m f, 6 v sanyo d c4, c5, c11, c12, c23, c26, c27, std capacitor, ceramic, 0.1 m f, 16 v sanyo 603 c7, c22 std capacitor, ceramic, 1 m f, 16 v sanyo 805 c9 std open 1210 c10, c16 std open 603 c14, c15 std open d c17, c24 std capacitor, ceramic, 1000 pf, 16 v sanyo 603 c18, c19 std capacitor, ceramic, 1 m f, 16 v sanyo 805 d1 sml-lx2832g diode, led, green, 2.1 v sm lumwx 1210 l1, l2 do3316p-332 inductor, 3.3 m h, 5.4 a coilcraft 0.5 0.37 in j1 ed2227 terminal block, 4-pin, 15 a, 5.08 mm ost 5.08 mm j2 ed1515 terminal block, 3-pin, 6 a, 3.5 mm ost n, 6 a, jp1, jp2 s1132-3-nd header, right straight, 3-pin, 0.1 ctrs, 0.3o pins sullins #s1132-3-nd jp1shunt 929950-00-nd shunt jumper, 0.1o (for jp1) 3m 0.1o j3 s1132-2-nd header, right straight, 2-pin, 0.1 ctrs, 0.3o pins sullins #s1132-2-nd q1 open so-8 q2:a, q4, q5 irf7811 mosfet, n-ch, 30 v, 10 m w so-8 q2:b open to220 q3 2n7002dict-n mosfet, n-ch, 115 ma, 1.2 w diodes, inc. to-236 r3 std resistor, 10 kohms, 5 % 603 r4 std resistor, 1 kohms, 1% 603 r5 std resistor, 0 ohms, 1% 603 r6 std resistor, 1 kohms, 1% 603 r7 std resistor, 3.32 kohms, 1% 603 r8 std resistor, 10 ohms, 5 % 603 r9 std resistor, 2.7 ohms, 5 % 1206 r10 std resistor, 150 ohms, 5 % 603 r11 std resistor, 100 ohms, 1 % 603 r12 std resistor, 10 kohms, 5 % 603 r13 std resistor, 20.0 kohms, 1 % 603 r14 std resistor, 0 ohms, 5% 603 r15 std resistor, open 603 r16 std resistor, 15 kohms, 5 % 805 tp1tp10 240345 test point, red farnell tp11 131424400 adaptor, 3.5-mm probe clip (or 131503100) tektronix u1 tps56302pwp dual controller tssop28pin
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 31 post office box 655303 ? dallas, texas 75265 application information + power supply 5v, 5a supply load + 0 4 a 6.8 ohms 2 w jumper pins 23 note a: all wire pairs should be twisted. figure 31. test setup
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 32 post office box 655303 ? dallas, texas 75265 application information dsp power application in dsp power applications, tps56302 is used in the applications that require more current for peripheral and dsp i/o. the power good (pg) output can be used for monitoring or controlling as an optional function. in the evm schematic, q3, d1, r1, and r2 are the circuit to show this function. v in rr output ldo output core i/o peripheral pg output (optional) ripple regulator ldo dsp figure 32. tps56302 for high peripheral current dsp application TPS56300 is used in the applications that require high current for core, but low current for i/o. another important feature is that, if the input voltage is the same as the ldo output, the ldo switch acts as a distribution switch to control the on/off of the ldo output. ripple regulator ldo core i/o dsp rr output ldo output v in pg output (optional) figure 33. TPS56300 for on/off control dsp application
tps56302 dual-output low-input-voltage dsp power supply controller with sequencing slvs289 march 2000 33 post office box 655303 ? dallas, texas 75265 mechanical data pwp (r-pdso-g**) powerpad ? plastic small-outline package 4073225/e 03/97 0,50 0,75 0,25 0,15 nom thermal pad (see note d) gage plane 28 24 7,70 7,90 20 6,40 6,60 9,60 9,80 6,60 6,20 11 0,19 4,50 4,30 10 0,15 20 a 1 0,30 1,20 max 16 14 5,10 4,90 pins ** 4,90 5,10 dim a min a max 0,05 seating plane 0,65 0,10 m 0,10 0 8 20-pin shown notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusions. d. the package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. this pad is electric ally and thermally connected to the backside of the die and possibly selected leads. e. falls within jedec mo-153 powerpad is a trademark of texas instruments.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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